MAX1184ECM+TD【PDF 6/21 页】IC ADC 10BIT 20MSPS DL 48-TQFP

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MAX1184

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

______________________________________________________________________________________

Table 1. MAX1184 Output Codes For Differential Inputs

*VREF = VREFP - VREFN

DIFFERENTIAL INPUT

VOLTAGE*

DIFFERENTIAL

INPUT

STRAIGHT OFFSET

BINARY

T/B = 0

TWO’S COMPLEMENT

T/B = 1

VREF x 511/512

+FULL SCALE - 1LSB

11 1111 1111

01 1111 1111

VREF x 1/512

+ 1 LSB

10 0000 0001

00 0000 0001

Bipolar Zero

10 0000 0000

00 0000 0000

- VREF x 1/512

- 1 LSB

01 1111 1111

11 1111 1111

-VREF x 511/512

- FULL SCALE + 1 LSB

00 0000 0001

10 0000 0001

-VREF x 512/512

- FULL SCALE

00 0000 0000

10 0000 0000

The output coding can be chosen to be either straight

offset binary or two’s complement (Table 1) controlled

by a single pin (T/B). Pull T/B low to select offset binary

and high to activate two’s complement output coding.

The capacitive load on the digital outputs D0A–D9A

and D0B–D9B should be kept as low as possible

(<15pF) to avoid large digital currents that could feed

back into the analog portion of the MAX1184, thereby

degrading its dynamic performance. Using buffers on

the digital outputs of the ADCs can further isolate the

digital outputs from heavy capacitive loads. To further

improve the dynamic performance of the MAX1184,

small-series resistors (e.g., 100

) may be added to the

digital output paths close to the MAX1184.

Figure 4 displays the timing relationship between out-

put enable and data output valid as well as power-

down/wake-up and data output valid.

Power-Down (PD) and

Sleep (SLEEP) Modes

The MAX1184 offers two power-save modes—sleep and

full power-down mode. In sleep mode (SLEEP = 1), only

the reference bias circuit is active (both ADCs are dis-

abled), and current consumption is reduced to 2.8mA.

To enter full power-down mode, pull PD high. With OE

simultaneously low, all outputs are latched at the last

value prior to the power down. Pulling OE high forces

the digital outputs into a high-impedance state.

Applications Information

Figure 5 depicts a typical application circuit containing

two single-ended to differential converters. The internal

reference provides a VDD/2 output voltage for level-shift-

ing purposes. The input is buffered and then split to a

voltage follower and inverter. One lowpass filter per ADC

suppresses some of the wideband noise associated with

high-speed op amps follows the amplifiers. The user may

select the RISO and CIN values to optimize the filter per-

formance, to suit a particular application. For the applica-

tion in Figure 5, a RISO of 50

is placed before the

capacitive load to prevent ringing and oscillation. The

22pF CIN capacitor acts as a small bypassing capacitor.

OUTPUT

D9A–D0A

tDISABLE

tENABLE

HIGH-Z

VALID DATA

OUTPUT

D9B–D0B

HIGH-Z

VALID DATA

Figure 4. Output Timing Diagram

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